Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
SyncSim extensions: simulation with VHDL and code generation
2006 (English)Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

SyncSim is a simulator framework capable of loading different simulator modules. It is used today with a module that simulates hardware models described with Java. This simulator module is used together with a model of a MIPS processor core in courses given at EISLAB. The purpose of this thesis is to create a new simulator module for SyncSim which can use hardware models described with a mixture of VHDL and Java and to implement a C compiler that can generate code compatible with the existing MIPS model. EESim is a simulator module for an early version of SyncSim that uses VHDL to describe the hardware model. This simulator module will be extended to meet the requirements of the new simulator. The Portable C Compiler (PCC) has previously been released as open source and work has been done by others to modernize it. PCC will be ported to the MIPS architecture and its portability evaluated. The result is a new version of EESim that can simulate models which mix VHDL and Java, and a PCC port capable of producing MIPS assembly code. With regards to portability PCC was found to be relatively easy to modify for use on a new computer architecture.

Place, publisher, year, edition, pages
2006.
Keyword [en]
Technology, SyncSim, PCC, MIPS, VHDL
Keyword [sv]
Teknik
Identifiers
URN: urn:nbn:se:ltu:diva-51855ISRN: LTU-EX--06/041--SELocal ID: 90802933-0dc4-41a7-8061-15da6e50d49dOAI: oai:DiVA.org:ltu-51855DiVA: diva2:1025219
Subject / course
Student thesis, at least 30 credits
Educational program
Computer Science and Engineering, master's level
Examiners
Note
Validerat; 20101217 (root)Available from: 2016-10-04 Created: 2016-10-04Bibliographically approved

Open Access in DiVA

fulltext(817 kB)22 downloads
File information
File name FULLTEXT01.pdfFile size 817 kBChecksum SHA-512
c73a8c631a5b231d701f2cc8c667382beee659130653e4cc047e7930efe7bf441cf5202a779514eca01c884b50a007a69501cee35b1b3ca71848f50999d2c23b
Type fulltextMimetype application/pdf

Search outside of DiVA

GoogleGoogle Scholar
Total: 22 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

urn-nbn

Altmetric score

urn-nbn
Total: 37 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf