Change search
ReferencesLink to record
Permanent link

Direct link
Hardware design of a network address translator
2002 (English)Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

In this thesis a design of Network Address Translator (NAT) for handling flow based translation of Transmission Control Protocol (TCP) for Internet Protocol version 4 (IPv4) is investigated. In flow based the data stream is terminated and restarted on the other side. The design is suited for a hardware implementation which implies several problems. TCP Checksum, TCP Timers, Retransmission, Sliding window and a scalable number of connections are some problems and all have been solved. Other more basic parts of TCP has also been solved and a reasonable TCP standard have been achieved. To implement the design in Hardware Description Language (HDL) to fit into a FPGA has not been achieved. In order to do so, restructuring of some core architecture is needed.

Place, publisher, year, edition, pages
Keyword [en]
Technology, Network Address Translator, NAT
Keyword [sv]
URN: urn:nbn:se:ltu:diva-51273ISRN: LTU-EX--02/093--SELocal ID: 87c64b65-9587-4eac-9c65-29bc05aea42eOAI: diva2:1024634
Subject / course
Student thesis, at least 30 credits
Educational program
Computer Science and Engineering, master's level
Validerat; 20101217 (root)Available from: 2016-10-04 Created: 2016-10-04Bibliographically approved

Open Access in DiVA

fulltext(400 kB)0 downloads
File information
File name FULLTEXT01.pdfFile size 400 kBChecksum SHA-512
Type fulltextMimetype application/pdf

Search outside of DiVA

GoogleGoogle Scholar
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

ReferencesLink to record
Permanent link

Direct link