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Hardware design of a network address translator
2002 (English)Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

In this thesis a design of Network Address Translator (NAT) for handling flow based translation of Transmission Control Protocol (TCP) for Internet Protocol version 4 (IPv4) is investigated. In flow based the data stream is terminated and restarted on the other side. The design is suited for a hardware implementation which implies several problems. TCP Checksum, TCP Timers, Retransmission, Sliding window and a scalable number of connections are some problems and all have been solved. Other more basic parts of TCP has also been solved and a reasonable TCP standard have been achieved. To implement the design in Hardware Description Language (HDL) to fit into a FPGA has not been achieved. In order to do so, restructuring of some core architecture is needed.

Place, publisher, year, edition, pages
2002.
Keyword [en]
Technology, Network Address Translator, NAT
Keyword [sv]
Teknik
Identifiers
URN: urn:nbn:se:ltu:diva-51273ISRN: LTU-EX--02/093--SELocal ID: 87c64b65-9587-4eac-9c65-29bc05aea42eOAI: oai:DiVA.org:ltu-51273DiVA: diva2:1024634
Subject / course
Student thesis, at least 30 credits
Educational program
Computer Science and Engineering, master's level
Examiners
Note
Validerat; 20101217 (root)Available from: 2016-10-04 Created: 2016-10-04Bibliographically approved

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Type fulltextMimetype application/pdf

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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf