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Downlink baseband decoder implementation
2008 (English)Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Previous generations of cellular networks was built for telephone calls and slow data transmission. Due to the rapid changes in information technology, these factors do not meet the requirements of today's wireless revolution. The first specifications for the 3rd generation system (3G) was released 2000 from the 3GPP collaboration group. WCDMA is one of the air interfaces in the specifications. In 2001 the first phase of HSDPA, High Speed Downlink Packet Access, was introduced to the specifications. Instead of sending the data on a dedicated channel to each user the radio resources are used more efficiently in HSDPA by using shared channels in the downlink. A control channel signals which users that is to receive data in each time instance. This master thesis has been carried out at DBP IoV (Downlink Baseband Processing Integration and Verification) at Ericsson, Lindholmen in Gothenburg. This department is responsible for realtime target integration and verification of the baseband processing system in WCDMA, including testenvironment development and testcase design. Currently tests are in most cases executed and recorded for offline analysis. The memory available for recording on the test hardware limits the maximum run-time of the tests. To be able to run long tests data has to be decoded and analyzed in real-time. The purpose of this thesis was to design and implement a realtime decoder for a subset of WCDMA, namely the downlink HSDPA channels. It should be investigated how much that can be done in software on a DSP and how much, if at all, that needs to be done in hardware on an FPGA. This was then to be implemented on and integrated into existing test environments. A comprehensive study of WCDMA in general and HSDPA in particular has been carried out. The specifications define in detail how encoding is done, so the core part of the thesis was to design a decoder based on these. During the project there was a need to verify parts of the implementation so an encoder was programmed in Matlab, enabling control of all parameters. It was concluded that decoding could be done entirely on the DSP, and a working decoder software was made. This does however have limitations in the number of users (mobiles) in the system and only supports one cell. If some of the processing is emigrated to hardware (FPGA) these limitations could easily be overcome.

Place, publisher, year, edition, pages
Keyword [en]
Technology, 3G, WCDMA, HSDPA, DSP, Real-Time Decoder
Keyword [sv]
URN: urn:nbn:se:ltu:diva-51005ISRN: LTU-EX--08/010--SELocal ID: 83b6f44a-b128-4c88-89f1-723267c022deOAI: diva2:1024368
Subject / course
Student thesis, at least 30 credits
Educational program
Electrical Engineering, master's level
Validerat; 20101217 (root)Available from: 2016-10-04 Created: 2016-10-04Bibliographically approved

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