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Look-up table FPGA synthesis from minimized multi-valued pseudo Kronecker expressions
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
Institute of Computer Science, Albert-Ludwigs-University.
Institute of Computer Science, Albert-Ludwigs-University.
1998 (English)In: Proceedings: 28th IEEE International Symposium on Multiple-Valued Logic, May 27 - 29, 1998, Fukuoka, Japan / [ed] Tsutomu Sasao; Bob Werner, Los Alamitos, Calif: IEEE Communications Society, 1998, p. 95-100Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we outline a method for Look-up Table-FPGA (LUT-FPGA) synthesis from minimized Multi-Valued Pseudo Kronecker Expressions (MV PSDKROs). By restricting logic minimization to consider only easily mappable expressions, a regular Cellular Architecture (CA) layout without routing overhead is obtained. In this way our method combines logic minimization, mapping and routing. The transformation into the MV domain reduces the area as the number of products in the PSDKRO expression can be further minimized. Deriving the exact minimum MV PSDKRO is known to be hard or even intractable. We address this by applying pruning techniques based on cost estimation and dynamic methods to find suitable variable orderings. Results on a set of MCNC benchmarks show the advantages of the proposed minimization methods

Place, publisher, year, edition, pages
Los Alamitos, Calif: IEEE Communications Society, 1998. p. 95-100
National Category
Embedded Systems
Research subject
Embedded System
Identifiers
URN: urn:nbn:se:ltu:diva-39482DOI: 10.1109/ISMVL.1998.679310Local ID: e419c550-120a-11dd-ada4-000ea68e967bISBN: 0-8186-8371-6 (print)OAI: oai:DiVA.org:ltu-39482DiVA, id: diva2:1012995
Conference
IEEE International Symposium on Multiple-Valued Logic : 27/05/1998 - 29/05/1998
Note
Godkänd; 1998; 20080424 (ysko)Available from: 2016-10-03 Created: 2016-10-03 Last updated: 2017-11-25Bibliographically approved

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