Switching activity estimation of finite state machines for low power synthesis
2002 (English)In: Proceedings: 2002 IEEE International Symposium on Circuits and Systems : May 26 - 29, 2002, Fairmont Scottsdale Princess, Phoenix-Scottsdale, Arizona, U.S.A., Piscataway, NJ: IEEE Communications Society, 2002, 65-68 p.Conference paper (Refereed)
A technique for computing the switching activity of synchronous finite state machine (FSM) implementations including the influence of temporal correlation among the next state signals is described. The approach is based upon the computation that a FSM is in a given state which, in turn, is used to compute the conditional probability that a next state bit changes given its present state value. All computations are performed using decision diagram (DD) data structures. As an application of this method, the next state activity information is utilized for low power optimization in the synthesis of binary decision diagram (BDD) mapped circuits. Experimental results are presented based on a set of the ISCAS89 sequential benchmarks showing an average power reduction of 40 percent and tip to 90 percent reduction for individual benchmarks on the estimated power dissipation.
Place, publisher, year, edition, pages
Piscataway, NJ: IEEE Communications Society, 2002. 65-68 p.
Research subject Embedded System
IdentifiersURN: urn:nbn:se:ltu:diva-39271DOI: 10.1109/ISCAS.2002.1010389Local ID: def76cd0-0bbb-11dd-9b51-000ea68e967bISBN: 0-7803-7448-7OAI: oai:DiVA.org:ltu-39271DiVA: diva2:1012781
IEEE International Symposium on Circuits and Systems : 26/05/2002 - 29/05/2002
Godkänd; 2002; 20080416 (cira)2016-10-032016-10-03Bibliographically approved