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Low power optimization technique for BDD mapped circuits
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
Luleå tekniska universitet.
Mississippi State University.
University of Freiburg.
2001 (English)In: Proceedings of the ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001: January 30 - February 2, 2001, Pacifico Yokohama, Yokohama, Japan, Piscataway, NJ: IEEE Communications Society, 2001, 615-621 p.Conference paper (Refereed)
Abstract [en]

The minimization of power consumption is an important design constraint for circuits used in portable devices. The switching activity of a circuit node in a CMOS digital circuit directly contributes to overall power dissipation. By approximating the switching activity of circuit nodes as internal switching probabilities in binary decision diagrams (BDDs), it is possible to estimate the dynamic power dissipation characteristic of circuits resulting from a structural mapping of a BDD. A technique for minimizing the overall sum of switching probabilities is presented. The method is based on efficient local operations on a BDD representing the functionality of the circuit to be realized. The resulting circuit that is obtained by mapping the BDD to CMOS pass transistors has in simulation (using a commercially available process model) shown reduced power dissipation characteristic. Experimental results on a set of MCNC benchmarks are given for this technique

Place, publisher, year, edition, pages
Piscataway, NJ: IEEE Communications Society, 2001. 615-621 p.
Research subject
Embedded System
URN: urn:nbn:se:ltu:diva-32642DOI: 10.1109/ASPDAC.2001.913377Local ID: 733359f0-9c43-11dd-94de-000ea68e967bISBN: 0-7803-6633-6OAI: diva2:1005876
Asia and South Pacific Design Automation Conference : 30/01/2001 - 02/02/2001
Godkänd; 2001; 20081017 (ysko)Available from: 2016-09-30 Created: 2016-09-30Bibliographically approved

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