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Execution of neural network algorithms on an array of bit-serial processors
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Signals and Systems.
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Signals and Systems.
1990 (English)In: Proceedings, 10th International Conference on Pattern Recognition, Piscataway, NJ: IEEE Communications Society, 1990, p. 501-505Conference paper (Refereed)
Abstract [en]

Large processor arrays are candidates for performing computations of neural network models at speeds required for real time applications, e.g. in pattern recognition. The paper gives a general model of an array of bit-serial processors and demonstrates the mapping of neural net models on such an array. The approach maps a neuron on each processing element and makes communication all-to-all available by connection weight matrices. The required communication structure is very simple. The bit-serial approach allows trade-offs between speed and precision, even dynamically. Performance figures are given. A bitserial multiplier is an important part of the design. Implementation aspects are discussed and it is shown that a one-board realization of a 1024 processor system is feasible with current, commonly available, technology.

Place, publisher, year, edition, pages
Piscataway, NJ: IEEE Communications Society, 1990. p. 501-505
National Category
Signal Processing
Research subject
Signal Processing
Identifiers
URN: urn:nbn:se:ltu:diva-32474DOI: 10.1109/ICPR.1990.119410Local ID: 6fab7520-12ae-11dd-ada4-000ea68e967bISBN: 0-8186-2062-5 (print)OAI: oai:DiVA.org:ltu-32474DiVA, id: diva2:1005708
Conference
International Conference on Pattern Recognition : Computer Architectures for Vision and Pattern Recognition 16/06/1990 - 21/06/1990
Note

Godkänd; 1990; 20080425 (ysko)

Available from: 2016-09-30 Created: 2016-09-30 Last updated: 2017-12-18Bibliographically approved

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