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Symbolic cycle simulation with closure detection towards symbolic verification
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
1996 (English)In: Proceedings of the Synthesis and System Integration of Mixed Technologies: SASIMI 96, 1996Conference paper, Published paper (Refereed)
Abstract [en]

We describe the algorithms for symbolic cycle simulation of sequential designs containing hierarchies of icompletely specified functions and Boolean relations. We propose the SSTG (symbolic state transition graph), which captures both the propagation of unknown input values and the effect of icomplerteness in the specification, and we develop algorithms for SSTG closure detection. Input vectors can be presented as Boolean relations, both spatial and temporal, on previous sets of input vectors, internal states and output vectors. Moreover the SSTG can be used towards verifying the correctness of the design with repect to both synthesis and redesign.

Place, publisher, year, edition, pages
1996.
National Category
Embedded Systems
Research subject
Embedded System
Identifiers
URN: urn:nbn:se:ltu:diva-30187Local ID: 3ee71440-12a8-11dd-ada4-000ea68e967bOAI: oai:DiVA.org:ltu-30187DiVA: diva2:1003414
Conference
Workshop on Synthesis And System Integration of MIxed technologies : 25/11/1996 - 26/11/1996
Note
Godkänd; 1996; 20080425 (ysko)Available from: 2016-09-30 Created: 2016-09-30 Last updated: 2017-11-25Bibliographically approved

Open Access in DiVA

fulltext(2271 kB)