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Synthesis of pseudo Kronecker lattice diagrams
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
1999 (English)In: Proceedings. Reed-Muller99: International Workshop on Applications of the Reed-Muller Expansion in Circuit Design, 1999Conference paper, Published paper (Refereed)
Abstract [en]

The design process of digital circuits is often carried out in individual steps, like logic minimization, mapping and routing. This leads to quality loss e.g., in cases where highly optimized netlists fit badly onto the target architecture. Lattice diagrams have been proposed as one possible solution. They offer a regular two dimensional structure, thus overcoming the routing problem. However elegant, presented methods have only shown to find practical lattice representations for small functions. We present heuristic synthesis methods for Pseudo-Symmetric Pseudo Kronecker Decision Diagrams (PSPKDDs) applicable to incompletely specified multiple output functions. The lattice structure maps directly to both ASICs and fine grain FPGAs. Our method (combining logic minimization, mapping and routing) seeks to minimize area and delay by heuristic methods. Experimental results on a set of MCNC benchmarks show superior quality to previous methods and in many cases even optimal depth results for unfolded lattices.

Place, publisher, year, edition, pages
1999.
National Category
Embedded Systems
Research subject
Embedded System
Identifiers
URN: urn:nbn:se:ltu:diva-28452Scopus ID: 33300432Local ID: 24118090-12aa-11dd-ada4-000ea68e967bOAI: oai:DiVA.org:ltu-28452DiVA: diva2:1001649
Conference
International Workshop on Applications of the Reed-Muller Expansion in Circuit Design : 20/08/1999 - 21/08/1999
Note
Godkänd; 1999; 20080425 (ysko)Available from: 2016-09-30 Created: 2016-09-30 Last updated: 2017-11-25Bibliographically approved

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CiteExportLink to record
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