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High throughput architecture for OCTAGON network on chip
KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar. Ohio State University, United States . (RaMSiS Group)
2009 (engelsk)Inngår i: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, IEEE , 2009, s. 101-104Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

High Throughput Octagon architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increase. The throughput oy the network by 17% while preservin. The average latency. The area of High Throughput OCTAGON switch is decreased by 18% as compared to OCTAGON switch. The total metal resources required to implement High Throughput OCTAGON design is increased by 8% as compared to the total metal resources required to implement OCTAGON design. The extra power consumption required to achiev. The proposed architecture is 2% oy the total power consumption oy the OCTAGON architecture.

sted, utgiver, år, opplag, sider
IEEE , 2009. s. 101-104
Emneord [en]
Latency, Noc, OCTAGON, Throughput
HSV kategori
Identifikatorer
URN: urn:nbn:se:kth:diva-152414DOI: 10.1109/ICECS.2009.5410933Scopus ID: 2-s2.0-77951459701ISBN: 978-142445091-6 (tryckt)OAI: oai:DiVA.org:kth-152414DiVA, id: diva2:752010
Konferanse
2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, 13 December 2009 through 16 December 2009, Yasmine Hammamet, Tunisia
Merknad

QC 20141002

Tilgjengelig fra: 2014-10-02 Laget: 2014-09-26 Sist oppdatert: 2022-06-23bibliografisk kontrollert

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Totalt: 1378 treff
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