Silicon pixel detectors are at the core of the current and planned upgrade of the ATLAS experiment at the LHC. Given their close proximity to the interaction point, these detectors will be exposed to an unprecedented amount of radiation over their lifetime. The current pixel detector will receive damage from non-ionizing radiation in excess of 10(15) 1 MeV n(eq)/cm(2), while the pixel detector designed for the high-luminosity LHC must cope with an order of magnitude larger fluence. This paper presents a digitization model incorporating effects of radiation damage to the pixel sensors. The model is described in detail and predictions for the charge collection efficiency and Lorentz angle are compared with collision data collected between 2015 and 2017 (<= 10(15) 1 MeV n(eq)/cm(2)).

Silicon Pixel detectors are at the core of the current and planned upgrade of the ATLAS detector. As the detector in closest proximity to the interaction point, these detectors will be exposed to a significant amount of radiation over their lifetime: before the High Luminosity phase of the Large Hadron Collider (HL-LHC) the innermost layers will receive a fluence in excess of 1015 neq/cm2 and the HL-LHC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. This work presents the details of a new simulation model that includes radiation damage effects to the 3D Pixel sensors for the ATLAS detector.

The increased particle collision rate following the upgrade of the Large Hadron Collider (LHC) to an increased luminosity requires an increased readout data speed, especially for the ATLAS pixel detector, located closest to the particle interaction point. For this reason, during the Phase-II upgrade of the ATLAS experiment the output data speed of the pixel front-end chips will be increased from 160 Mbps to 5 Gbps. The increased radiation levels will require a radiation hard data transmission link to be designed to carry this data from the pixel front-end to the off-detector system where it will undergo optical conversion. We propose a receiver utilizing the concept of Decision Feedback Equalization (DFE) to be used in this link, where the number of filter taps can be determined from simulations using S-parameter data from measurements of various customized cable prototypes under characterization as candidates to function as transmission medium between the on-chip data driver and the receiver of the link. A dedicated framework has been set up in Matlab to analyze the S-parameter characteristics for the various cable prototypes and investigate the possibilities for signal recovery and maintained signal integrity using DFE, as well as pre-emphasis and different encoding schemes. The simulation results indicate that DFE could be an excellent choice for expanding the system bandwidth to reach required data speeds with minimal signal distortion.

This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has four upstream receiver channels and a downstream transmitter channel. Each upstream channel operates at 5.12 Gbps, while the downstream channel operates at 2.56 Gbps. In each upstream channel, GBCR equalizes a signal received through a 5-meter 34-American Wire Gauge (AWG) twin-axial cable, retimes the data with a recovered clock, and drives an optical transmitter. In the downstream channel, GBCR receives the data from an optical receiver and drives the same type of cable as the upstream channels. The output jitter of an upstream channel is 26.5 ps and the jitter of the downstream channel after the cable is 33.5 ps. Each upstream channel consumes 78 mW and each downstream channel consumes 27 mW. Simulation results of the upstream test channel suggest that a significant jitter reduction could be achieved with minimally increased power consumption by using a Feed Forward Equalizer (FFE) + Decision Feedback Equalization (DFE) in addition to the linear equalization of the baseline channel. GBCR is designed in a 65-nm CMOS technology.