In order to enable the ATLAS experiment to successfully track charged particles produced in high-energy collisions at the High-Luminosity Large Hadron Collider, the current ATLAS Inner Detector will be replaced by the Inner Tracker (ITk), entirely composed of silicon pixel and strip detectors. An extension of the tracking coverage of the ITk to very forward pseudorapidity values is proposed, using pixel modules placed in a long cylindrical layer around the beam pipe. The measurement of long pixel clusters, detected when charged particles cross the silicon sensor at small incidence angles, has potential to significantly improve the tracking efficiency, fake track rejection, and resolution of the ITk in the very forward region. The performance of state-of-the-art pixel modules at small track incidence angles is studied using test beam data collected at SLAC and CERN.

A pixel readout test chip called FE65-P2 has been fabricated on 65 nm CMOS technology. FE65-P2 contains a matrix of 64 x 64 pixels on 50 micron by 50 micron pitch, designed to read out a bump bonded sensor. The goals of FE65-P2 are to demonstrate excellent analog performance isolated from digital activity well enough to achieve 500 electron stable threshold, be radiation hard to at least 500 Mrad, and prove the novel concept of isolated analog front ends embedded in a flat digital design, dubbed “analog islands in a digital sea”. Experience from FE65-P2 and hybrid assemblies will be applied to the design for a large format readout chip, called RD53A, to be produced in a wafer run in early 2017 by the RD53 collaboration. We review the case for 65 nm technology and report on threshold stability test results for the FE65-P2.

Silicon pixel detectors are at the core of the current and planned upgrade of the ATLAS experiment at the LHC. Given their close proximity to the interaction point, these detectors will be exposed to an unprecedented amount of radiation over their lifetime. The current pixel detector will receive damage from non-ionizing radiation in excess of 10(15) 1 MeV n(eq)/cm(2), while the pixel detector designed for the high-luminosity LHC must cope with an order of magnitude larger fluence. This paper presents a digitization model incorporating effects of radiation damage to the pixel sensors. The model is described in detail and predictions for the charge collection efficiency and Lorentz angle are compared with collision data collected between 2015 and 2017 (<= 10(15) 1 MeV n(eq)/cm(2)).

Following the advent of a post-Moore’s law field of computation, novel architectures continue to emerge. With composite, multi-million connection neuromorphic chips like IBM’s TrueNorth, neural engineering has now become a feasible technology in this novel computing paradigm. High Energy Physics experiments are continuously exploring new methods of computation and data handling, including neuromorphic, to support the growing challenges of the field and be prepared for future commodity computing trends. This work details the first instance of a Kalman filter implementation in IBM’s neuromorphic architecture, TrueNorth, for both parallel and serial spike trains. The implementation is tested on multiple simulated systems and its performance is evaluated with respect to an equivalent non-spiking Kalman filter. The limits of the implementation are explored whilst varying the size of weight and threshold registers, the number of spikes used to encode a state, size of neuron block for spatial encoding, and neuron potential reset schemes.