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Germanium on Insulator Fabrication for Monolithic 3-D Integration
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0002-2397-2588
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0003-0568-0984
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2018 (English)In: IEEE Journal of the Electron Devices Society, E-ISSN 2168-6734, Vol. 6, no 1, p. 588-593Article in journal (Refereed) Published
Abstract [en]

A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC , 2018. Vol. 6, no 1, p. 588-593
Keywords [en]
GOI, wafer bonding, selective etching, GOI MOSFET, 3D integration
National Category
Materials Chemistry
Identifiers
URN: urn:nbn:se:kth:diva-231645DOI: 10.1109/JEDS.2018.2801335ISI: 000435505000007Scopus ID: 2-s2.0-85041650674OAI: oai:DiVA.org:kth-231645DiVA, id: diva2:1245065
Funder
Swedish Foundation for Strategic Research
Note

QC 20211004

Available from: 2018-09-04 Created: 2018-09-04 Last updated: 2023-02-06Bibliographically approved
In thesis
1. Applications of Si1-xGex alloys for Ge devices and monolithic 3D integration
Open this publication in new window or tab >>Applications of Si1-xGex alloys for Ge devices and monolithic 3D integration
2020 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

As the semiconductor industry moves beyond the 10 nm node, power consumption constraints and reduction of the negative impact of parasitic elements become important. Silicon germanium (Si1−xGex) alloys have been used to amplify the performance of Si based devices and integrated circuits (ICs) for decades. Selective epitaxial growth of heavily doped Si and/or Si1−xGex is commonly employed to reduce the effect of parasitic resistance. Reducing the supply voltage leads to lower dynamic power consumption in complementary metal-oxide-semiconductor (CMOS) technology. Monolithic three-dimensional integration (M3D) is a technology that employs vertical stacking of the device tiers. This approach reduces the wiring length, effectively reducing interconnect delay, load capacitance and ultimately reducing the power consumption. Among the integration challenges M3D is facing, one can distinguish the available thermal budget for fabrication, the crystalline quality of the device active layer and finally the actual device or circuit performance.Germanium channel devices can benefit M3D integration. Germanium metal-oxide-semiconductor field-effect transistors (MOSFETs) can be fabricated at significantly lower temperatures than Si. In addition, they potentially can have higher performance compared to Si due to the superior electron and hole mobilities of Ge. Active layer transfer of crystalline quality layers is a key step in a M3D fabrication flow. Direct wafer bonding techniques offerthe possibility to transfer a Ge layer on a patterned wafer. This thesis studies the various applications of Si1−xGex films in M3D. An initial implementation of an in situ doped Si1−xGex film on silicon-on-insulator (SOI) and germanium substrates is first presented. A Si1−xGex film isgrown selectively on SOI substrates to be used as a contact electrode on Si nanowire biosensors. On Ge bulk substrates, in situdoped Si1−xGex is epitaxially grown to form p+-n junctions. The junction leakage current and the mechanisms at play are studied. The analysis ofthe junction performance provides insights on the junction leakage mechanisms,an important issue for the implementation of in situ doped Si1−xGex in M3D. A low temperature germanium-on-insulator (GOI) fabrication flow based on room temperature wafer bonding and etch back is presented in this work. The method suggested in the thesis produces high quality, crystalline Ge device layers with excellent uniformity. The thesis also reports on the development and integration of Si1−xGex in the GOI fabrication as an etch stop layer, enabling the stability of the layer transfer process. Finally this thesis presents Ge p-channel field-effect transistor (PFET) devices fabricated on the previously developed GOI substrates.The technologies presented in this thesis can be integrated in large scale Ge device fabrication. The low temperature GOI and Ge PFET fabrication methods are very well suited for sequential device fabrication. The processes and applications presented in this thesis meet the current thermal budget, device performance and active layer transfer demands for M3D technology.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2020. p. 87
Series
TRITA-EECS-AVL ; 2020:5
Keywords
Silicon, germanium, epitaxy, selective, pn junction, germanium on insulator, GOI, Ge PFET, bonding, monolithic, sequential, three dimensional, 3D, low temperature
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Information and Communication Technology
Identifiers
urn:nbn:se:kth:diva-269412 (URN)978-91-7873-465-8 (ISBN)
Public defence
2020-04-03, Join Zoom Meeting https://kth-se.zoom.us/j/664249709, 13:00 (English)
Opponent
Supervisors
Funder
Swedish Foundation for Strategic Research , 66197
Note

QC 20200310

Disputation via Zoom (Campus closed)

Join Zoom Meeting

https://kth-se.zoom.us/j/664249709

Available from: 2020-03-10 Created: 2020-03-06 Last updated: 2022-06-26Bibliographically approved
2. Germanium layer transfer and device fabrication for monolithic 3D integration
Open this publication in new window or tab >>Germanium layer transfer and device fabrication for monolithic 3D integration
2021 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Monolithic three-dimensional (M3D) integration, it has been proposed,can overcome the limitations of further circuits’ performance improvementand functionality expansion. The emergence of the internet of things (IoT) isdriving the semiconductor industry toward the fabrication of higher-performancecircuits with diverse functionality. On the one hand, the scaling of devices isreaching critical dimensions, which makes their further downscaling techno-logically difficult and economically challenging, whereas, on the other hand,the field of electronics is no longer limited only to developing circuits thatare meant for data processing. Sensors, processors, actuators, memories, andeven power storage units need to be efficiently integrated into a single chip tomake IoT work. M3D integration through stacking different layers of deviceson each other can potentially improve circuits’ performance by shorteningthe wiring length and reducing the interconnect delay. Using multiple tiersfor device fabrication makes it possible to integrate different materials withsuperior physical properties. It offers the advantage of fabricating higher-performance devices with multiple functionalities on a single chip. However,high-quality layer transfer and processing temperature budget are the majorchallenges in M3D integration. This thesis involves an in-depth explorationof the application of germanium (Ge) in monolithic 3D integration.Ge has been recognized as one of the most promising materials that canreplace silicon (Si) as the channel material for p-type field-effect transistors(pFETs) because of its high hole mobility. Ge pFETs can be fabricated atsubstantially lower temperatures compared to Si devices which makes theformer a good candidate for M3D integration. However, the fabrication ofhigh-quality Ge-on-insulator (GOI) layers with superior thickness homogene-ity, low residual doping, and a sufficiently good interface with buried oxide(BOX) has been challenging.This thesis used low-temperature wafer bonding and etch-back techniquesto fabricate the GOI substrate for M3D applications. For this purpose, aunique stack of epitaxial layers was designed and fabricated. The layer stackcontains a Ge strain relaxed buffer (SRB) layer, a SiGe layer to be used asan etch stop, and a top Ge layer to be transferred to the handling wafer.The wafers were bonded at room temperature, and the sacrificial wafer wasremoved through multiple etching steps leaving 20 nm Ge on the insulatorwith excellent thickness homogeneity over the wafer. Ge pFET devices werefabricated on the GOI substrates and electrically characterized to evaluatethe layer quality. Finally, the epitaxial growth of the highly doped SiGeand sub-nm Si cap layers have been investigated as alternatives for improvedperformance Ge pFETs.The Ge buffer layer was developed through the two-step deposition tech-nique resulting in defect density of107cm−3and surface roughness of 0.5 nm.The fully strainedSi0.5Ge0.5film with high crystal quality was epitaxiallygrown at temperatures below 450°C. The layer was sandwiched between theGe buffer and the top 20 nm Ge layer to be used as an etch-stop in the etch- back process. A highly selective etching method was developed to remove the3μm Ge buffer and 10nm SiGe film without damaging the 20 nm transferringGe layer.The Ge pFETs were fabricated at temperatures below 600°C so that theycould be compatible with the M3D integration. The back interface of thedevices depleted atVBG= 0V, which confirmed the small density of fixedcharges at the Ge/BOX interface along with a low level of residual doping inthe Ge channel. The Ge pFETs with 70 % yield over the whole wafer showed60 % higher carrier mobility than Si reference devices.Low-temperature epitaxial growth of Si passivation layer on Ge was de-veloped in this thesis. For electrical evaluation of the passivation layer,metal-oxide-semiconductor (MOS) capacitors were fabricated and character-ized. The capacitors showed an interface trap density of3×1011eV−1cm−2,and hysteresis as low as 3 mV at Eox of 4MV/cm corresponding to oxide trapdensity of1.5×1010cm−2. The results indicate that this Si passivation layersubstantially improves the gate dielectric by reducing the subthreshold slopeof Ge devices while increasing their reliability. The in-situ doped SiGe layerwith a dopant concentration of2.5×1019cm−3and resistivity of 3.5 mΩcmwas selectively grown on Ge to improve the junction formation.The methods developed in this thesis are suitable for large-scale M3Dintegration of Ge pFET devices on the Si platform. The unique Ge layertransfer and etch-back techniques resulted in the fabrication of GOI substrateswith high thickness homogeneity, low residual doping, and sufficiently goodGe/BOX interface. The process temperatures for Ge transfer and pFETsfabrication are kept within the range of the M3D budget. Integration of theSi cap for gate dielectric formation and SiGe layers in the source/drain regionmay increase device performance and reliability

Abstract [sv]

Sakernas internet (eng. Internet of Things, IoT) driver halvledarindustrinmot tillverkning av högprestanda komponenter och kretsar med flertal funk-tionaliteter. Å ena sidan skalas komponenter ned till storlekar där ytterligarenedskalning blir teknologiskt svårt och ekonomiskt utmanande. Å andra si-dan är dagens elektronik inte längre begränsad till kretsar för databehandling.För att sakernas internet ska fungera behöver sensorer, processorer, styrdon,datorminne och även energilagringsenheter integreras på ett effektivt sätt i ge-mensamma chip. Monolitisk 3-dimensionell integration (M3D) baseras på attstapla olika komponentnivåer på varandra. Detta tillvägagångssätt är en avdem mest lovande metoderna för att förbättra kretsarnas prestanda. Prestan-dan förbättras genom att förkorta elektriska ledare och minska fördröjningen iledarna. Att ha flera komponentnivåer möjliggör integration av komponenter,som kan använda sig av olika material med högkvalitetsegenskaper för olikatillämpningar och funktioner, i ett enda chip. De stora utmaningarna för M3Där högkvalitétsöverföring av skikt och begränsad processtemperatursbudget.Germanium (Ge) anses vara det bästa materialet för att ersätta kisel (Si) somkanalmaterial i p-typs fälteffektstransistorer (pFET) tack vare dess höga hål-mobilitet. Vidare anses germanium lovande för M3D-integration tack germa-niumtransistorernas jämförelsevisa låga processtemperatur mot motsvarandekiseltransistorer. Dock har tillverkning av germanium-på-isolator (eng. germa-nium on insulator, GOI) flera utmaningar: tjockleken på germaniumskiktetmåste vara jämnt över skivan, dopningen måste vara låg och gränssnittet motden begravda oxiden (eng. buried oxide, BOX) måste vara tillräckligt god.I denna avhandling används skivbondning vid låg temperatur och tillbaka-etsför att tillverka GOI-substrat för M3D-tillämpningar. En unik stapling av epi-taxiellt växta skikt har designats och tillverkats för detta ändamål. Skiktstap-lingen innehåller ett relaxerad bufferskikt av germanium, ett etsstoppsskiktav kiselgermanium (SiGe) och ett toppskikt av germanium som i slutändanöverförs till en hanteringsskiva. Skivorna direktbondas vid rumstemperatur,och offerskivan togs bort genom flera etssteg som lämnar 20 nm germanium påisolator med utmärkt tjockleksjämnhet över skivan. Germaniumtransistorertillverkades på GOI-substrat och mättes elektriskt för att utvärdera skiktkva-litén. Epitaxiellt växt av högdopat SiGe och sub-nanometer kiseltäckeskikt(eng. silicon cap layer) utforskades som alternativ för germaniumtransistorermed förbättrad prestanda.Bufferskikt av germanium togs fram med två-stegs deponeringsteknik vilketgav resultatet att defekttätheten var107cm−3och ytruffighet var 0,5 nm.TöjtSi0,5Ge0,5-skikt med hög kristallkvalité växtes epitaxiellt vid tempera-turer lägre än 450°C. Skiktet, som infogades mellan bufferskiktet av germa-nium och toppskiktet av 20-nm tjockt germanium, användes som etsstoppi tillbaka-etsprocessen. En mycket selektiv etsmetod utvecklades för att tabort den 3-μm tjocka bufferskiktet av germanium och den 10-nm tjockaSi0,5Ge0,5-skiktet utan att skada den 20-nm tjocka germaniumtoppskiktet.För att tillverkningen av germaniumtransistorerna ska var kompatibla medM3D-integration så tillverkades dem vid en temperatur lägre än 600°C. Kom- ponentens baksidesgränsnitt (Ge/BOX-gränssnittet) var utarmat vidVBG=0V, vilket bekräftar att både den fixa laddningstätheten vid gränssnittet ochdopningen var lågt. Germaniumtransistorerna hade 70 % avkastning över helaskivan och uppvisade 60 % högre kanalmobilitet än motsvarande komponenteri kisel. In-situ dopat SiGe-skikt med dopningskoncentration på2.5×1019cm−3och resistivitet på 3.5 mcm växtes selektivt på germanium för att förbättrakäll- och dräneringsövergångsbildningen. Den unika staplingen av grinddie-lektrikaGe/Si/T mSiO/T m2O3/Hf O2/T iNsom togs fram i denna avhand-ling uppvisade en gränssnittsfälltäthet på3×1011eV−1cm−2och en hyste-res på låga 3 mV vid ett pålagt elektriskt fält över grinddielektrikastapelnpå 4 MV/cm, vilket motsvarar en oxidfälltäthet på1.5×1010cm−2. Dessaresultat visar att denna grinddielektrikastapel kan potentiellt minska germa-niumtransistorernas undertröskelsving samtidigt som den förbättrar tillförlit-ligheten. Metoderna som har tagits fram i denna avhandling är lämpliga förstorskalig M3D-integration av germaniumtransistorer på en kiselplattform.Den unika skiktöverföringmetoden av germanium och tillbaka-ets teknikenresulterade i tillverkningen av GOI-substrat med god tjockleksjämnhet, lågdopning och tillräckligt god Ge/BOX-gränssnitt. Processtemperaturerna förgermanium-överföring och transistortillverkning hålls inom ramarna för M3D-integrationens temperaturbudget. Integration av SiGe-skikt i käll/dränerings-områden och kiseltäcket för grinddielektrikumbildning kan öka komponent-prestanda och tillförlitlighet.

Place, publisher, year, edition, pages
KTH Royal Institute of Technology, 2021. p. 97
Series
TRITA-EECS-AVL ; 2021:23
Keywords
Monolithic, sequential, 3D, silicon, germanium, wafer bonding, etch back, germanium on insulator, GOI, Ge pFET, low temperature, Sipassivation, pn junction, Kisel, germanium, epitaxi, selektiv, pn-övergång, germanium påisolator, GOI, Ge PFET, bonding, monolitisk, sekventiell, tre dimensionell, 3D, lågtemperarad
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-293970 (URN)978-91-7873-834-2 (ISBN)
Public defence
2021-05-21, Sal-C, Kistagången 16, 16440 Kista, Stockholm, 13:00 (English)
Opponent
Supervisors
Funder
Swedish Foundation for Strategic Research Swedish Research Council
Note

QC 20210506

Available from: 2021-05-06 Created: 2021-05-06 Last updated: 2022-06-25Bibliographically approved
3. Ge/high-k Gates for Monolithic 3D Integration
Open this publication in new window or tab >>Ge/high-k Gates for Monolithic 3D Integration
2021 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Continuous scaling of transistor dimensions has been in the heart of semiconductorindustry for many years. Recently the scaling has been enabled by various performance boosters which resulted in increased processing complexity and cost, forcing the chip manufacturers to look for some alternative solutions. Monolithic 3D integration has been identified as a promising candidate for future CMOS technology nodes, as it could enable a further increasein device density through stacking tiers of older and cheaper generation transistorson top of each other. One of the major challenges faced by monolithic 3D integration is the thermal budget during upper tier fabrication since high temperature steps used in conventional CMOS processing can damage the bottom tier devices. To this respect, Ge has an advantage over Si due to its intrinsically low processing temperature. However, realizing Ge devices that provide performance and reliability comparable to Si devices is not straight forward. Gate stack formation in Ge devices is particularly challenging, as Ge lacks a stable oxide for surface passivation.

In this work, gate stack solutions for Ge-based devices for monolithic 3D integration applications have been extensively studied. Low temperature Ge surface passivation with GeOx and Si-cap process has been investigated and characterized in terms of interface state density, oxide trap density and fixed charge density. GeOx has been integrated with other high-k dielectrics, suchas Al2O3, Tm2O3 and HfO2, and with the help of post deposition and forming gas treatments provided sufficient surface passivation with low interface state density. However, devices with GeOx passivation suffered from poor reliability stemming from the lack of thermal stability and high oxide trap density in GeOx layer. On the other hand, Si-cap integrated with TmSiO interfacial layer has been shown to provide both low interface trap density and oxide trap density, albeit within a narrow process window for Si-cap growth conditions. Selected gate stacks with GeOx and Si-cap passivation have been integrated in Ge pFET process on in-house fabricated germanium on insulator substrates. Subthreshold slope values inline with previous reports have been achieved, as well as 60 % higher hole mobility than in reference silicon on insulator pFETs. Moreover, initial results of Si-cap and TmSiO interfacial layer integration ingermanium on insulator nFETs have been demonstrated.

This work presents both advantages and limitations of each gate stacksolution on Ge platform. The processes employed in this work are monolithic 3D integration compatible, and demonstrate that with some process optimization Ge transistors could be integrated on Si platform in monolithic3D integration fashion.

Abstract [sv]

Kontinuerlig nedskalning av transistorers dimensioner har varit A och O för halvledarindustrin. Den senaste nedskalningen har möjliggjorts tack vare olika prestandaförbättrare, men med dessa förbättrare har tillverkningskostnad och komplexitet ökat, vilket har lett till att chiptillverkare måste söka efter alternativa lösningar. En lovande kandidat för framtida teknologinoder är monolitisk 3D integration, där fördelen är att transistortätheten ökas genom att stapla transistorer från tidigare och billigare teknologinoder på varandra. En av de stora utmaningarna för monolitisk 3D integration är att värmebudgeten är begränsad för de övre transistorskikten eftersom att höga temperaturer, vilket krävs i konventionell transistortillverkning, kommer att förstöratransistor på de lägre skikten. Germaniumtransistorer har intrinsiskt en fördel mot kiseltransistorer i detta avseende då tillverkningen kan ske vid lägre temperatur. Dock är det utmanande att tillverka germaniumtransistorer som har prestanda och tillförlitlighet som är jämförbar med den som kiseltransistorer har. Gate-stapeltillverkningen för germaniumtransistorer är synnerligen utmanande då germanium saknar en stabil oxid som passiverar ytan.

I detta arbete har lösningar till gate-tillverkningen för germaniumtransistorer för monolitisk 3D integration undersökts utförligt. Lågtemperaturprocesser för ytpassivering av germanium med germaniumoxid (GeOx) och kiselskikt (eng. Si-cap) har undersökts och karaktäriserats med avseende på tätheten på gränssnittsdefekter, fälltäthet i oxiden och fixa laddningstäthet. GeOx har integrerats tillsammans med hög-permittivitetsdielektrika, såsomaluminiumoxid (Al2O3), tuliumoxid (Tm2O3) och hafniumoxid (HfO2), och m.h.a. post-deponerings- och formgasbehandling kunde ytan passiveras tillräckligtför att uppnå en låg täthet av gränssnittsdefekter. Dock led komponenter med GeOx-passivering av dålig tillförlitlighet p.g.a. bristande termisk stabilitet och en hög fälltäthet i GeOx-skiktet. Å andra sidan uppvisade kiselskikt integrerat med ett gränssnittsskikt av tuliumsilikat (TmSiO) både låg gränssnittsfälltäthet och oxidfälltäthet, förvisso inom ett snävt tillverkningsfönster för kiselskikt tillväxt. Några utvalda gate-processer med GeOx och kiselskiktspassivering har implementerats i tillverkningsflödet för p-typ germaniumtransistorer på germanium-på-isolator substrat. Subtröskelskarakteristik som är jämförbara med värden i litteraturen har uppnåtts samt 60% högre hålkanalsmobilitet jämfört med referens-kiseltransistorer på kisel-på-isolator substrat. Utöver detta presenteras preliminära resultat från n-typ germaniumtransistorer med kiselskiktspassivering och ett gränssnittsskikt av tuliumsilikat.

Detta arbete presenterar både fördelar och begränsningar för varje gatestapellösning för germaniumplattformen. Processflödena som har använts i detta arbete är kompatibla med monolitisk 3D integration, och med processoptimering kan germaniumtransistorer integreras på en kiselplattform via monolitisk 3D integration.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2021. p. 81
Series
TRITA-EECS-AVL ; 2021:60
Keywords
Germanium, high-k, monolithic, 3D, germanium on insulator, GOI, germanium oxide, GeOx, Si-cap, Si-passivation, interface state density, Dit, low temperature, MOSFET, germanium, hög-permittivitetsdielektrika, monolitisk, 3D, germaniumpå- isolator, GOI, germaniumoxid, GeOx, kiselskikt, kiselpassivering, gränssnittsfälltäthet, Dit, låg temperatur, MOSFET
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Information and Communication Technology
Identifiers
urn:nbn:se:kth:diva-302649 (URN)978-91-7873-996-7 (ISBN)
Public defence
2021-10-22, Zoom: https://kth-se.zoom.us/j/62697101332?pwd=bm1Ld0duTWtUQ1puR2t1UXNtN2g4QT09, Sal C, Kistagången 16, Kista, 09:00 (English)
Opponent
Supervisors
Funder
Swedish Foundation for Strategic Research
Note

QC 20210930

Available from: 2021-09-30 Created: 2021-09-28 Last updated: 2022-06-25Bibliographically approved

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