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Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density
KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.ORCID-id: 0000-0002-2397-2588
KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.ORCID-id: 0000-0003-0568-0984
KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.ORCID-id: 0000-0001-6705-1660
Vise andre og tillknytning
2016 (engelsk)Inngår i: ECS Transactions, Electrochemical Society, 2016, nr 8, s. 615-621Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with carrier mobility enhancement. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.

sted, utgiver, år, opplag, sider
Electrochemical Society, 2016. nr 8, s. 615-621
Emneord [en]
Chemical vapor deposition, Silicon, Silicon alloys, Strain relaxation, Surface defects, Surface roughness, Surface topography, Temperature, Defects density, Low-dislocation density, Low-temperature grown, Mobility enhancement, Reduced pressure chemical vapor deposition, Strain relaxed buffers, Strain-relaxed, Threading dislocation densities, Germanium
HSV kategori
Identifikatorer
URN: urn:nbn:se:kth:diva-201995DOI: 10.1149/07508.0615ecstISI: 000578410100061Scopus ID: 2-s2.0-84991585471ISBN: 9781607685395 (tryckt)OAI: oai:DiVA.org:kth-201995DiVA, id: diva2:1077049
Konferanse
Symposium on SiGe, Ge, and Related Materials: Materials, Processing, and Devices 7 - PRiME 2016/230th ECS Meeting, 2 October 2016 through 7 October 2016
Merknad

QC 20170224

Tilgjengelig fra: 2017-02-24 Laget: 2017-02-24 Sist oppdatert: 2024-03-18bibliografisk kontrollert
Inngår i avhandling
1. Fabrication of Group IV Semiconductors on Insulator for Monolithic 3D Integration
Åpne denne publikasjonen i ny fane eller vindu >>Fabrication of Group IV Semiconductors on Insulator for Monolithic 3D Integration
2018 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

The conventional 2D geometrical scaling of transistors is now facing many challenges in order to continue the performance enhancement while decreasing power consumption. The decrease in the device power consumption is related to the scaling of the power supply voltage (Vdd) and interconnects wiring length. In addition, monolithic three dimensional (M3D) integration in the form of vertically stacked devices, is a possible solution to increase the device density and reduce interconnect wiring length. Integrating strained germanium on insulator (sGeOI) pMOSFETs monolithically with strained silicon/silicon-germanium on insulator (sSOI/sSiGeOI) nMOSFETs can increase the device performance and packing density. Low temperature processing (<550 ºC) is essential as interconnects and strained layers limit the thermal budget in M3D. This thesis presents an experimental investigation of the low temperature (<450 ºC) fabrication of group IV semiconductor-on-insulator substrates with the focus on sGeOI and sSiGeOI fabrication processes compatible with M3D.

  To this aim, direct bonding was used to transfer the relaxed and strained semiconductor layers. The void formation dependencies of the oxide thickness, the surface treatment of the oxide and the post annealing time were fully examined. Low temperature SiGe epitaxy was investigated with the emphasis on the fabrication of Si0.5Ge0.5 strain-relaxed buffers (SRBs), etch-stop layer, and the device layer in the SiGeOI and GeOI process schemes. Ge epitaxial growth on Si as thick SRBs and thin device layers was investigated. Thick (500 nm-3 µm) and thin (<30 nm) relaxed GeOI substrates were fabricated. The latter was fabricated by continuous epitaxial growth of a 3-µm Ge (SRB)/Si0.5Ge0.5 (etch stop)/Ge (device layer) stack on Si. The fabricated long channel Ge pFETs from these GeOI substrates exhibit well-behaved IV characteristics with an effective mobility of 160 cm2/Vs.

  The planarization of SiO2 and SiGe SRBs for the fabrication of the strained GeOI and SiGeOI were accomplished by chemical mechanical polishing (CMP). Low temperature processes (<450 ºC) were developed for compressively strained GeOI layers (ɛ ~ -1.75 %, < 20 nm), which are used for high mobility and low power devices. For the first time, tensile strained Si0.5Ge0.5 (ɛ ~ 2.5 %, < 20 nm) films were successfully fabricated and transferred onto patterned substrates for 3D integration.

sted, utgiver, år, opplag, sider
Kungliga Tekniska högskolan, 2018. s. 139
Serie
TRITA-EECS-AVL ; 2018:01
Emneord
monolithic three dimensional (M3D) integration, strained germanium on insulator (sGeOI) pMOSFETs, silicon/silicon-germanium on insulator (sSOI/sSiGeOI) nMOSFETs, Si0.5Ge0.5 strain-relaxed buffer (SRB), direct bonding, chemical mechanical polishing (CMP), compressively strained GeOI, tensile strained Si0.5Ge0.5OI
HSV kategori
Identifikatorer
urn:nbn:se:kth:diva-221097 (URN)978-91-7729-658-4 (ISBN)
Disputas
2018-02-16, Ka-Sal C, Electrum, Kungliga Tekniska högskolan, Kistagången 16, Kista, Stockholm, 10:00 (engelsk)
Opponent
Veileder
Merknad

QC 20180115

Tilgjengelig fra: 2018-01-15 Laget: 2018-01-12 Sist oppdatert: 2022-06-26bibliografisk kontrollert
2. Applications of Si1-xGex alloys for Ge devices and monolithic 3D integration
Åpne denne publikasjonen i ny fane eller vindu >>Applications of Si1-xGex alloys for Ge devices and monolithic 3D integration
2020 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

As the semiconductor industry moves beyond the 10 nm node, power consumption constraints and reduction of the negative impact of parasitic elements become important. Silicon germanium (Si1−xGex) alloys have been used to amplify the performance of Si based devices and integrated circuits (ICs) for decades. Selective epitaxial growth of heavily doped Si and/or Si1−xGex is commonly employed to reduce the effect of parasitic resistance. Reducing the supply voltage leads to lower dynamic power consumption in complementary metal-oxide-semiconductor (CMOS) technology. Monolithic three-dimensional integration (M3D) is a technology that employs vertical stacking of the device tiers. This approach reduces the wiring length, effectively reducing interconnect delay, load capacitance and ultimately reducing the power consumption. Among the integration challenges M3D is facing, one can distinguish the available thermal budget for fabrication, the crystalline quality of the device active layer and finally the actual device or circuit performance.Germanium channel devices can benefit M3D integration. Germanium metal-oxide-semiconductor field-effect transistors (MOSFETs) can be fabricated at significantly lower temperatures than Si. In addition, they potentially can have higher performance compared to Si due to the superior electron and hole mobilities of Ge. Active layer transfer of crystalline quality layers is a key step in a M3D fabrication flow. Direct wafer bonding techniques offerthe possibility to transfer a Ge layer on a patterned wafer. This thesis studies the various applications of Si1−xGex films in M3D. An initial implementation of an in situ doped Si1−xGex film on silicon-on-insulator (SOI) and germanium substrates is first presented. A Si1−xGex film isgrown selectively on SOI substrates to be used as a contact electrode on Si nanowire biosensors. On Ge bulk substrates, in situdoped Si1−xGex is epitaxially grown to form p+-n junctions. The junction leakage current and the mechanisms at play are studied. The analysis ofthe junction performance provides insights on the junction leakage mechanisms,an important issue for the implementation of in situ doped Si1−xGex in M3D. A low temperature germanium-on-insulator (GOI) fabrication flow based on room temperature wafer bonding and etch back is presented in this work. The method suggested in the thesis produces high quality, crystalline Ge device layers with excellent uniformity. The thesis also reports on the development and integration of Si1−xGex in the GOI fabrication as an etch stop layer, enabling the stability of the layer transfer process. Finally this thesis presents Ge p-channel field-effect transistor (PFET) devices fabricated on the previously developed GOI substrates.The technologies presented in this thesis can be integrated in large scale Ge device fabrication. The low temperature GOI and Ge PFET fabrication methods are very well suited for sequential device fabrication. The processes and applications presented in this thesis meet the current thermal budget, device performance and active layer transfer demands for M3D technology.

sted, utgiver, år, opplag, sider
Stockholm: KTH Royal Institute of Technology, 2020. s. 87
Serie
TRITA-EECS-AVL ; 2020:5
Emneord
Silicon, germanium, epitaxy, selective, pn junction, germanium on insulator, GOI, Ge PFET, bonding, monolithic, sequential, three dimensional, 3D, low temperature
HSV kategori
Forskningsprogram
Informations- och kommunikationsteknik
Identifikatorer
urn:nbn:se:kth:diva-269412 (URN)978-91-7873-465-8 (ISBN)
Disputas
2020-04-03, Join Zoom Meeting https://kth-se.zoom.us/j/664249709, 13:00 (engelsk)
Opponent
Veileder
Forskningsfinansiär
Swedish Foundation for Strategic Research , 66197
Merknad

QC 20200310

Disputation via Zoom (Campus closed)

Join Zoom Meeting

https://kth-se.zoom.us/j/664249709

Tilgjengelig fra: 2020-03-10 Laget: 2020-03-06 Sist oppdatert: 2022-06-26bibliografisk kontrollert
3. Germanium layer transfer and device fabrication for monolithic 3D integration
Åpne denne publikasjonen i ny fane eller vindu >>Germanium layer transfer and device fabrication for monolithic 3D integration
2021 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

Monolithic three-dimensional (M3D) integration, it has been proposed,can overcome the limitations of further circuits’ performance improvementand functionality expansion. The emergence of the internet of things (IoT) isdriving the semiconductor industry toward the fabrication of higher-performancecircuits with diverse functionality. On the one hand, the scaling of devices isreaching critical dimensions, which makes their further downscaling techno-logically difficult and economically challenging, whereas, on the other hand,the field of electronics is no longer limited only to developing circuits thatare meant for data processing. Sensors, processors, actuators, memories, andeven power storage units need to be efficiently integrated into a single chip tomake IoT work. M3D integration through stacking different layers of deviceson each other can potentially improve circuits’ performance by shorteningthe wiring length and reducing the interconnect delay. Using multiple tiersfor device fabrication makes it possible to integrate different materials withsuperior physical properties. It offers the advantage of fabricating higher-performance devices with multiple functionalities on a single chip. However,high-quality layer transfer and processing temperature budget are the majorchallenges in M3D integration. This thesis involves an in-depth explorationof the application of germanium (Ge) in monolithic 3D integration.Ge has been recognized as one of the most promising materials that canreplace silicon (Si) as the channel material for p-type field-effect transistors(pFETs) because of its high hole mobility. Ge pFETs can be fabricated atsubstantially lower temperatures compared to Si devices which makes theformer a good candidate for M3D integration. However, the fabrication ofhigh-quality Ge-on-insulator (GOI) layers with superior thickness homogene-ity, low residual doping, and a sufficiently good interface with buried oxide(BOX) has been challenging.This thesis used low-temperature wafer bonding and etch-back techniquesto fabricate the GOI substrate for M3D applications. For this purpose, aunique stack of epitaxial layers was designed and fabricated. The layer stackcontains a Ge strain relaxed buffer (SRB) layer, a SiGe layer to be used asan etch stop, and a top Ge layer to be transferred to the handling wafer.The wafers were bonded at room temperature, and the sacrificial wafer wasremoved through multiple etching steps leaving 20 nm Ge on the insulatorwith excellent thickness homogeneity over the wafer. Ge pFET devices werefabricated on the GOI substrates and electrically characterized to evaluatethe layer quality. Finally, the epitaxial growth of the highly doped SiGeand sub-nm Si cap layers have been investigated as alternatives for improvedperformance Ge pFETs.The Ge buffer layer was developed through the two-step deposition tech-nique resulting in defect density of107cm−3and surface roughness of 0.5 nm.The fully strainedSi0.5Ge0.5film with high crystal quality was epitaxiallygrown at temperatures below 450°C. The layer was sandwiched between theGe buffer and the top 20 nm Ge layer to be used as an etch-stop in the etch- back process. A highly selective etching method was developed to remove the3μm Ge buffer and 10nm SiGe film without damaging the 20 nm transferringGe layer.The Ge pFETs were fabricated at temperatures below 600°C so that theycould be compatible with the M3D integration. The back interface of thedevices depleted atVBG= 0V, which confirmed the small density of fixedcharges at the Ge/BOX interface along with a low level of residual doping inthe Ge channel. The Ge pFETs with 70 % yield over the whole wafer showed60 % higher carrier mobility than Si reference devices.Low-temperature epitaxial growth of Si passivation layer on Ge was de-veloped in this thesis. For electrical evaluation of the passivation layer,metal-oxide-semiconductor (MOS) capacitors were fabricated and character-ized. The capacitors showed an interface trap density of3×1011eV−1cm−2,and hysteresis as low as 3 mV at Eox of 4MV/cm corresponding to oxide trapdensity of1.5×1010cm−2. The results indicate that this Si passivation layersubstantially improves the gate dielectric by reducing the subthreshold slopeof Ge devices while increasing their reliability. The in-situ doped SiGe layerwith a dopant concentration of2.5×1019cm−3and resistivity of 3.5 mΩcmwas selectively grown on Ge to improve the junction formation.The methods developed in this thesis are suitable for large-scale M3Dintegration of Ge pFET devices on the Si platform. The unique Ge layertransfer and etch-back techniques resulted in the fabrication of GOI substrateswith high thickness homogeneity, low residual doping, and sufficiently goodGe/BOX interface. The process temperatures for Ge transfer and pFETsfabrication are kept within the range of the M3D budget. Integration of theSi cap for gate dielectric formation and SiGe layers in the source/drain regionmay increase device performance and reliability

Abstract [sv]

Sakernas internet (eng. Internet of Things, IoT) driver halvledarindustrinmot tillverkning av högprestanda komponenter och kretsar med flertal funk-tionaliteter. Å ena sidan skalas komponenter ned till storlekar där ytterligarenedskalning blir teknologiskt svårt och ekonomiskt utmanande. Å andra si-dan är dagens elektronik inte längre begränsad till kretsar för databehandling.För att sakernas internet ska fungera behöver sensorer, processorer, styrdon,datorminne och även energilagringsenheter integreras på ett effektivt sätt i ge-mensamma chip. Monolitisk 3-dimensionell integration (M3D) baseras på attstapla olika komponentnivåer på varandra. Detta tillvägagångssätt är en avdem mest lovande metoderna för att förbättra kretsarnas prestanda. Prestan-dan förbättras genom att förkorta elektriska ledare och minska fördröjningen iledarna. Att ha flera komponentnivåer möjliggör integration av komponenter,som kan använda sig av olika material med högkvalitetsegenskaper för olikatillämpningar och funktioner, i ett enda chip. De stora utmaningarna för M3Där högkvalitétsöverföring av skikt och begränsad processtemperatursbudget.Germanium (Ge) anses vara det bästa materialet för att ersätta kisel (Si) somkanalmaterial i p-typs fälteffektstransistorer (pFET) tack vare dess höga hål-mobilitet. Vidare anses germanium lovande för M3D-integration tack germa-niumtransistorernas jämförelsevisa låga processtemperatur mot motsvarandekiseltransistorer. Dock har tillverkning av germanium-på-isolator (eng. germa-nium on insulator, GOI) flera utmaningar: tjockleken på germaniumskiktetmåste vara jämnt över skivan, dopningen måste vara låg och gränssnittet motden begravda oxiden (eng. buried oxide, BOX) måste vara tillräckligt god.I denna avhandling används skivbondning vid låg temperatur och tillbaka-etsför att tillverka GOI-substrat för M3D-tillämpningar. En unik stapling av epi-taxiellt växta skikt har designats och tillverkats för detta ändamål. Skiktstap-lingen innehåller ett relaxerad bufferskikt av germanium, ett etsstoppsskiktav kiselgermanium (SiGe) och ett toppskikt av germanium som i slutändanöverförs till en hanteringsskiva. Skivorna direktbondas vid rumstemperatur,och offerskivan togs bort genom flera etssteg som lämnar 20 nm germanium påisolator med utmärkt tjockleksjämnhet över skivan. Germaniumtransistorertillverkades på GOI-substrat och mättes elektriskt för att utvärdera skiktkva-litén. Epitaxiellt växt av högdopat SiGe och sub-nanometer kiseltäckeskikt(eng. silicon cap layer) utforskades som alternativ för germaniumtransistorermed förbättrad prestanda.Bufferskikt av germanium togs fram med två-stegs deponeringsteknik vilketgav resultatet att defekttätheten var107cm−3och ytruffighet var 0,5 nm.TöjtSi0,5Ge0,5-skikt med hög kristallkvalité växtes epitaxiellt vid tempera-turer lägre än 450°C. Skiktet, som infogades mellan bufferskiktet av germa-nium och toppskiktet av 20-nm tjockt germanium, användes som etsstoppi tillbaka-etsprocessen. En mycket selektiv etsmetod utvecklades för att tabort den 3-μm tjocka bufferskiktet av germanium och den 10-nm tjockaSi0,5Ge0,5-skiktet utan att skada den 20-nm tjocka germaniumtoppskiktet.För att tillverkningen av germaniumtransistorerna ska var kompatibla medM3D-integration så tillverkades dem vid en temperatur lägre än 600°C. Kom- ponentens baksidesgränsnitt (Ge/BOX-gränssnittet) var utarmat vidVBG=0V, vilket bekräftar att både den fixa laddningstätheten vid gränssnittet ochdopningen var lågt. Germaniumtransistorerna hade 70 % avkastning över helaskivan och uppvisade 60 % högre kanalmobilitet än motsvarande komponenteri kisel. In-situ dopat SiGe-skikt med dopningskoncentration på2.5×1019cm−3och resistivitet på 3.5 mcm växtes selektivt på germanium för att förbättrakäll- och dräneringsövergångsbildningen. Den unika staplingen av grinddie-lektrikaGe/Si/T mSiO/T m2O3/Hf O2/T iNsom togs fram i denna avhand-ling uppvisade en gränssnittsfälltäthet på3×1011eV−1cm−2och en hyste-res på låga 3 mV vid ett pålagt elektriskt fält över grinddielektrikastapelnpå 4 MV/cm, vilket motsvarar en oxidfälltäthet på1.5×1010cm−2. Dessaresultat visar att denna grinddielektrikastapel kan potentiellt minska germa-niumtransistorernas undertröskelsving samtidigt som den förbättrar tillförlit-ligheten. Metoderna som har tagits fram i denna avhandling är lämpliga förstorskalig M3D-integration av germaniumtransistorer på en kiselplattform.Den unika skiktöverföringmetoden av germanium och tillbaka-ets teknikenresulterade i tillverkningen av GOI-substrat med god tjockleksjämnhet, lågdopning och tillräckligt god Ge/BOX-gränssnitt. Processtemperaturerna förgermanium-överföring och transistortillverkning hålls inom ramarna för M3D-integrationens temperaturbudget. Integration av SiGe-skikt i käll/dränerings-områden och kiseltäcket för grinddielektrikumbildning kan öka komponent-prestanda och tillförlitlighet.

sted, utgiver, år, opplag, sider
KTH Royal Institute of Technology, 2021. s. 97
Serie
TRITA-EECS-AVL ; 2021:23
Emneord
Monolithic, sequential, 3D, silicon, germanium, wafer bonding, etch back, germanium on insulator, GOI, Ge pFET, low temperature, Sipassivation, pn junction, Kisel, germanium, epitaxi, selektiv, pn-övergång, germanium påisolator, GOI, Ge PFET, bonding, monolitisk, sekventiell, tre dimensionell, 3D, lågtemperarad
HSV kategori
Identifikatorer
urn:nbn:se:kth:diva-293970 (URN)978-91-7873-834-2 (ISBN)
Disputas
2021-05-21, Sal-C, Kistagången 16, 16440 Kista, Stockholm, 13:00 (engelsk)
Opponent
Veileder
Forskningsfinansiär
Swedish Foundation for Strategic Research Swedish Research Council
Merknad

QC 20210506

Tilgjengelig fra: 2021-05-06 Laget: 2021-05-06 Sist oppdatert: 2022-06-25bibliografisk kontrollert

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