Ändra sökning
RefereraExporteraLänk till posten
Permanent länk

Direktlänk
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Annat format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annat språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf
Fabrication of Group IV Semiconductors on Insulator for Monolithic 3D Integration
KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik, Integrerade komponenter och kretsar. (EKT)ORCID-id: 0000-0002-0446-2515
2018 (Engelska)Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
Abstract [en]

The conventional 2D geometrical scaling of transistors is now facing many challenges in order to continue the performance enhancement while decreasing power consumption. The decrease in the device power consumption is related to the scaling of the power supply voltage (Vdd) and interconnects wiring length. In addition, monolithic three dimensional (M3D) integration in the form of vertically stacked devices, is a possible solution to increase the device density and reduce interconnect wiring length. Integrating strained germanium on insulator (sGeOI) pMOSFETs monolithically with strained silicon/silicon-germanium on insulator (sSOI/sSiGeOI) nMOSFETs can increase the device performance and packing density. Low temperature processing (<550 ºC) is essential as interconnects and strained layers limit the thermal budget in M3D. This thesis presents an experimental investigation of the low temperature (<450 ºC) fabrication of group IV semiconductor-on-insulator substrates with the focus on sGeOI and sSiGeOI fabrication processes compatible with M3D.

  To this aim, direct bonding was used to transfer the relaxed and strained semiconductor layers. The void formation dependencies of the oxide thickness, the surface treatment of the oxide and the post annealing time were fully examined. Low temperature SiGe epitaxy was investigated with the emphasis on the fabrication of Si0.5Ge0.5 strain-relaxed buffers (SRBs), etch-stop layer, and the device layer in the SiGeOI and GeOI process schemes. Ge epitaxial growth on Si as thick SRBs and thin device layers was investigated. Thick (500 nm-3 µm) and thin (<30 nm) relaxed GeOI substrates were fabricated. The latter was fabricated by continuous epitaxial growth of a 3-µm Ge (SRB)/Si0.5Ge0.5 (etch stop)/Ge (device layer) stack on Si. The fabricated long channel Ge pFETs from these GeOI substrates exhibit well-behaved IV characteristics with an effective mobility of 160 cm2/Vs.

  The planarization of SiO2 and SiGe SRBs for the fabrication of the strained GeOI and SiGeOI were accomplished by chemical mechanical polishing (CMP). Low temperature processes (<450 ºC) were developed for compressively strained GeOI layers (ɛ ~ -1.75 %, < 20 nm), which are used for high mobility and low power devices. For the first time, tensile strained Si0.5Ge0.5 (ɛ ~ 2.5 %, < 20 nm) films were successfully fabricated and transferred onto patterned substrates for 3D integration.

Ort, förlag, år, upplaga, sidor
Kungliga Tekniska högskolan, 2018. , s. 139
Serie
TRITA-EECS-AVL ; 2018:01
Nyckelord [en]
monolithic three dimensional (M3D) integration, strained germanium on insulator (sGeOI) pMOSFETs, silicon/silicon-germanium on insulator (sSOI/sSiGeOI) nMOSFETs, Si0.5Ge0.5 strain-relaxed buffer (SRB), direct bonding, chemical mechanical polishing (CMP), compressively strained GeOI, tensile strained Si0.5Ge0.5OI
Nationell ämneskategori
Nanoteknik
Identifikatorer
URN: urn:nbn:se:kth:diva-221097ISBN: 978-91-7729-658-4 (digital)OAI: oai:DiVA.org:kth-221097DiVA, id: diva2:1173679
Disputation
2018-02-16, Ka-Sal C, Electrum, Kungliga Tekniska högskolan, Kistagången 16, Kista, Stockholm, 10:00 (Engelska)
Opponent
Handledare
Anmärkning

QC 20180115

Tillgänglig från: 2018-01-15 Skapad: 2018-01-12 Senast uppdaterad: 2018-01-19Bibliografiskt granskad
Delarbeten
1. A Study of Surface Treatments and Voids Formation in Low Temperature Wafer Bonding
Öppna denna publikation i ny flik eller fönster >>A Study of Surface Treatments and Voids Formation in Low Temperature Wafer Bonding
(Engelska)Manuskript (preprint) (Övrigt vetenskapligt)
Nationell ämneskategori
Annan elektroteknik och elektronik
Identifikatorer
urn:nbn:se:kth:diva-221090 (URN)
Anmärkning

QC 20180115

Tillgänglig från: 2018-01-12 Skapad: 2018-01-12 Senast uppdaterad: 2018-01-15Bibliografiskt granskad
2. Low Temperature SiGe Epitaxy Using SiH4-GeH4and Si2H6-Ge2H6 Gas Precursors
Öppna denna publikation i ny flik eller fönster >>Low Temperature SiGe Epitaxy Using SiH4-GeH4and Si2H6-Ge2H6 Gas Precursors
(Engelska)Ingår i: Journal of Solid State Science and TechnologyArtikel i tidskrift (Övrigt vetenskapligt) Submitted
Nationell ämneskategori
Annan elektroteknik och elektronik
Identifikatorer
urn:nbn:se:kth:diva-221091 (URN)
Anmärkning

QC 20180115

Tillgänglig från: 2018-01-12 Skapad: 2018-01-12 Senast uppdaterad: 2018-01-15Bibliografiskt granskad
3. Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density
Öppna denna publikation i ny flik eller fönster >>Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density
Visa övriga...
2016 (Engelska)Ingår i: ECS Transactions, Electrochemical Society, 2016, nr 8, s. 615-621Konferensbidrag, Publicerat paper (Refereegranskat)
Abstract [en]

Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with carrier mobility enhancement. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.

Ort, förlag, år, upplaga, sidor
Electrochemical Society, 2016
Nyckelord
Chemical vapor deposition, Silicon, Silicon alloys, Strain relaxation, Surface defects, Surface roughness, Surface topography, Temperature, Defects density, Low-dislocation density, Low-temperature grown, Mobility enhancement, Reduced pressure chemical vapor deposition, Strain relaxed buffers, Strain-relaxed, Threading dislocation densities, Germanium
Nationell ämneskategori
Elektroteknik och elektronik
Identifikatorer
urn:nbn:se:kth:diva-201995 (URN)10.1149/07508.0615ecst (DOI)2-s2.0-84991585471 (Scopus ID)9781607685395 (ISBN)
Konferens
Symposium on SiGe, Ge, and Related Materials: Materials, Processing, and Devices 7 - PRiME 2016/230th ECS Meeting, 2 October 2016 through 7 October 2016
Anmärkning

QC 20170224

Tillgänglig från: 2017-02-24 Skapad: 2017-02-24 Senast uppdaterad: 2018-01-15Bibliografiskt granskad
4. Fabrication of relaxed germanium on insulator via room temperature wafer bonding
Öppna denna publikation i ny flik eller fönster >>Fabrication of relaxed germanium on insulator via room temperature wafer bonding
Visa övriga...
2014 (Engelska)Ingår i: ECS Transactions: Volume 64, Cancun, Mexico, October 5 – 9, 2014 2014 ECS and SMEQ Joint International Meeting, Electrochemical Society, 2014, nr 6, s. 533-541Konferensbidrag, Publicerat paper (Refereegranskat)
Abstract [en]

We report on the fabrication of, high quality, monocrystalline relaxed Germanium with ultra-low roughness on insulator (GeOI) using low-temperature direct wafer bonding. We observe that a two-step epitaxially grown germanium film fabricated on silicon by reduced pressure chemical vapor deposition can be directly bonded to a SiO2 layer using a thin Al2O3 as bonding mediator. After removing the donor substrate silicon the germanium layer exhibits a complete relaxation without degradation in crystalline quality and no stress in the film. . The results suggest that the fabricated high quality GeOI substrate is a suitable platform for high performance device applications.

Ort, förlag, år, upplaga, sidor
Electrochemical Society, 2014
Serie
ECS Transactions, ISSN 1938-5862 ; 64
Nyckelord
Bonding, Chemical bonds, Chemical vapor deposition, Fabrication, Germanium, Silicon, Silicon alloys, Silicon oxides, Silicon wafers, Temperature, Crystalline quality, Direct wafer bonding, Epitaxially grown, Germanium on insulators, High performance devices, Low temperatures, Reduced pressure chemical vapor deposition, Room temperature
Nationell ämneskategori
Materialteknik
Identifikatorer
urn:nbn:se:kth:diva-160681 (URN)10.1149/06406.0533ecst (DOI)2-s2.0-84921260797 (Scopus ID)
Konferens
6th SiGe, Ge, and Related Compounds: Materials, Processing and Devices Symposium - 2014 ECS and SMEQ Joint International Meeting, Cancun, Mexico, 5 October 2014 through 9 October 2014
Anmärkning

QC 20150226

Tillgänglig från: 2015-02-26 Skapad: 2015-02-26 Senast uppdaterad: 2018-01-15Bibliografiskt granskad
5. Silicon nanowires integrated with CMOS circuits for biosensing application
Öppna denna publikation i ny flik eller fönster >>Silicon nanowires integrated with CMOS circuits for biosensing application
Visa övriga...
2014 (Engelska)Ingår i: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 98, s. 26-31Artikel i tidskrift (Refereegranskat) Published
Abstract [en]

We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N-2 pixels or test sites) and 8 input-output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20 nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

Nyckelord
Nanowire, Biosensing, SOI, CMOS, STL
Nationell ämneskategori
Annan elektroteknik och elektronik
Identifikatorer
urn:nbn:se:kth:diva-149200 (URN)10.1016/j.sse.2014.04.005 (DOI)000339149000006 ()2-s2.0-84902251547 (Scopus ID)
Forskningsfinansiär
EU, Europeiska forskningsrådet, 228229
Anmärkning

QC 20140818

Tillgänglig från: 2014-08-18 Skapad: 2014-08-18 Senast uppdaterad: 2018-01-15Bibliografiskt granskad
6. GOI fabrication for Monolithic 3D integration
Öppna denna publikation i ny flik eller fönster >>GOI fabrication for Monolithic 3D integration
(Engelska)Ingår i: Artikel i tidskrift (Övrigt vetenskapligt) Submitted
Nationell ämneskategori
Annan elektroteknik och elektronik
Identifikatorer
urn:nbn:se:kth:diva-221093 (URN)
Anmärkning

QC 20180115

Tillgänglig från: 2018-01-12 Skapad: 2018-01-12 Senast uppdaterad: 2018-01-15Bibliografiskt granskad

Open Access i DiVA

fulltext(10047 kB)134 nedladdningar
Filinformation
Filnamn FULLTEXT01.pdfFilstorlek 10047 kBChecksumma SHA-512
404fb7569f14301bf4e58f2bab74ce7ab116359aec14a37d5334d0e534fb499b4ad40775386e0dd2d21853de6c111f363d3b44ab0608f62a91ef895bd47f50ae
Typ fulltextMimetyp application/pdf

Sök vidare i DiVA

Av författaren/redaktören
Asadollahi, Ali
Av organisationen
Integrerade komponenter och kretsar
Nanoteknik

Sök vidare utanför DiVA

GoogleGoogle Scholar
Totalt: 134 nedladdningar
Antalet nedladdningar är summan av nedladdningar för alla fulltexter. Det kan inkludera t.ex tidigare versioner som nu inte längre är tillgängliga.

isbn
urn-nbn

Altmetricpoäng

isbn
urn-nbn
Totalt: 2101 träffar
RefereraExporteraLänk till posten
Permanent länk

Direktlänk
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Annat format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annat språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf