Digitala Vetenskapliga Arkivet

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Low voltage high-speed CMOS square-law composite transistor cell
Vise andre og tillknytning
2000 (engelsk)Inngår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 25, nr 3, s. 347-349Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to \V-t\ +2V(ds,sat) and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2 mu m N-well process with a 3 V supply are given.

sted, utgiver, år, opplag, sider
2000. Vol. 25, nr 3, s. 347-349
Emneord [en]
analog signal processing, CMOS, low voltage, composite transistor, multiplier
Identifikatorer
URN: urn:nbn:se:kth:diva-20091ISI: 000089798800018OAI: oai:DiVA.org:kth-20091DiVA, id: diva2:338784
Merknad
QC 20100525Tilgjengelig fra: 2010-08-10 Laget: 2010-08-10 Sist oppdatert: 2017-12-12bibliografisk kontrollert

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Ismail, Mohammed
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Analog Integrated Circuits and Signal Processing

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