Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Customizing Instruction Set Extensible Reconfigurable Processors using GPUs
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
Technical University of Munich, Germany.
Technical University of Munich, Germany.
Show others and affiliations
2012 (English)In: 25th International Conferennce on VLSI Design, Hyderabad, India, January 07-11, 2012., IEEE , 2012, 418-423 p.Conference paper, Published paper (Refereed)
Abstract [en]

Many reconfigurable processors allow their instruction sets to be tailored according to the performance requirements of target applications. They have gained immense popularity in recent years because of this flexibility of adding custom instructions. However, most design automation algorithms for instruction set customization (like enumerating and selecting the optimal set of custom instructions) are computationally intractable. As such, existing tools to customize instruction sets of extensible processors rely on approximation methods or heuristics. In contrast to such traditional approaches, we propose to use GPUs (Graphics Processing Units) to efficiently solve computationally expensive algorithms in the design automation tools for extensible processors. To demonstrate our idea, we choose a custom instruction selection problem and accelerate it using CUDA (CUDA is a GPU computing engine). Our CUDA implementation is devised to maximize the achievable speedups by various optimizations like exploiting on-chip shared memory and register usage. Experiments conducted on well known benchmarks show significant speedups over sequential CPU implementations as well as over multi-core implementations.

Place, publisher, year, edition, pages
IEEE , 2012. 418-423 p.
Series
VLSI Design : Proceedings / the ... International Conference on VLSI Design, ISSN 1063-9667
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-72205ISBN: 978-0-7695-4638-4 (print)ISBN: 978-1-4673-0438-2 (print)OAI: oai:DiVA.org:liu-72205DiVA: diva2:458264
Conference
25th International Conferennce on VLSI Design, Hyderabad, India, January 07-11, 2012.
Available from: 2011-11-22 Created: 2011-11-22 Last updated: 2013-09-10

Open Access in DiVA

No full text

Search in DiVA

By author/editor
Bordoloi, Unmesh D.Suri, BharathEles, PetruPeng, Zebo
By organisation
ESLAB - Embedded Systems LaboratoryThe Institute of Technology
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar

Total: 213 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf